This invention relates to testing of integrated circuit boards, panels of integrated circuit devices, liquid crystal display (LCD) panels and particularly active matrix LCD panels.
One of the challenges in testing panels such as liquid crystal display panels is to be able to handle compact arrays of very large numbers of pixels. Active matrix LCD panels are now being manufactured in volume with integrated drivers on the panel in connection with polysilicon TFT structures. In normal application the integrated drivers are clocked at the relatively high speed of several Megahertz in order to address all of the lines of a relatively high density display within the time set aside for a single frame.
The demand is growing to test large high-speed arrays in circuit panels. Specifically, there is a need to be able to examine many thousands of different individual voltage points in an array at high speeds and to be able to determine the relative logic states of the voltages so captured. One application is in circuit board subsystem testing or multi-chip module testing.
A technology is now available for examining large numbers of individual voltage points simultaneously. However, this technology, which employs voltage imaging using polymer dispersed liquid crystals (PDLC), is relatively slow in that signal changes of less than one or two milliseconds in switching time cannot be sensed in real time. What is needed is a technique for overcoming the relatively slow behavior of polymer dispersed liquid crystals in order to take advantage of the high density of the technology to analyze large arrays of high speed switched circuits.